![]() Transistors Q5 and Q6 make the ANDing of inputs A and B, and transistor Q7 supplies the ORing of the NOR output with the ANDed output. Transistors Q1, Q2, Q3, and Q4 comprise the NOR gate. A logic block diagram for the XOR circuit. The truth table for a two-input XOR circuit.įigure 6 shows a two-input logic diagram, and figure 7 shows a CMOS circuit to satisfy the Boolean equation.įigure 6. Table 6 shows the truth table for a two-input XOR circuit. The output of a two-input XOR circuit assumes the logic 1 state if one and only one input assumes the logic 1 state.Īn equivalent logic statement is: ”If B=1 and A=0, or if A=1 and B=0, then Y=1.” The truth table for a two-input OR circuit. Table 5 shows the truth table for the OR circuit. Then, it is a NOR gate followed by an inverter. The truth table for a two-input CMOS AND circuit.įigure 4 shows a CMOS two-input AND gate.Īn OR gate is a NOT-NOT-OR or NOT-NOR. Table 4 shows the truth table for an AND circuit. Then, it is just a NAND gate followed by an inverter. ![]() ![]() We can say that an AND gate is a NOT-NOT-AND or NOT-NAND. In these cases, the output is logic 0 which is consistent with the above truth table. With both inputs logic 1, Q3 and Q4 are “on,” and Q1 and Q2 are “off,” producing a logic 0 output that confirms the last row of the truth table.įor the two remaining input combinations, either Q1 is “off” and Q3 is “on” or Q2 is “off” and is Q4 “on”. This confirms the first row of the truth table above. When both inputs, A and B, are logic 0, Q1 and Q2 are “on,” and Q3 and Q4 are “off,” and the output is logic 1. N-channel transistors Q3 and Q4 are connected in parallel between the output and ground. P-channel transistors Q1 and Q2 are connected in series between +V and the output terminal. The outcomes for other input combinations are logic 0.įigure 3 shows a CMOS two-input NOR gate. The output of a NOR gate is logic 1 with logic 0 in both inputs. The truth table for a two-input NOR circuit. Table 3 shows the truth table for a NOR circuit. When one of the inputs is a logic “1” and the other one is a logic “0”, either Q3 is “off” and Q2 is “on” or Q4 is “off” and Q1 is “on.” The output in both cases is a logic “1,” validating the second and the third rows of the truth table. This is consistent with the first row of the truth table. With logic 0 in inputs A and B, Q3 and Q4 transistors are “off,” and Q1 and Q2 transistors are “on,” producing a logic 1 output. This condition happens when both inputs, A and B, are logic 1, confirming the lowest row in the above truth table. With Q3 and Q4 transistors ”on” and Q1 and Q2 transistors “off,” the output is a logic 0. ![]() N-channel transistors Q3 and Q4 are connected in series between the output terminal and ground. ![]() P-channel transistors Q1 and Q2 are connected in parallel between +V and the output terminal. The truth table for a two-input NAND circuit.įigure 2 shows a CMOS two-input NAND gate. Table 2 shows the truth table for a NAND circuit. The input is connected to the gate terminal of the two transistors, and the output is connected to both drain terminals.Īpplying +V (logic 1) to the input (Vi), transistor Q2 is “on,” and transistor Q1 remains “off.” Under this condition, the output voltage (Vo) is close to 0 V (logic 0).Ĭonnecting the input to ground (Vi = 0 V), transistor Q2 is “off,” and transistor Q1 is “on.” Now, the output voltage is close to +V (logic 1). Figure 1 shows a NOT gate employing two series-connected enhancement-type MOSFETS, one n-channel (NMOS) and one p-channel (PMOS). This article assumes a positive logic.Ī NOT gate reverses the input logic state. The most fundamental connections are the NOT gate, the two-input NAND gate, and the two-input NOR gate. Logic gates that are the basic building block of digital systems are created by combining a number of n- and p-channel transistors. ![]()
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